With continued demand for higher bandwidth in wire-line, optical and wireless data communications systems, the output signaling rates in transceivers under development presently approach 25 Gb/s range and beyond. At multi-GHz speeds the main channel impairments such as insertion loss and inter-channel crosstalk interference are dramatically increased, presenting considerable challenge for the receiver data recovery and demanding application of advanced adaptive signal processing algorithms to achieve near-optimal reception. While such adaptive processing methods and algorithms are well described in the literature and readily implementable in the digital domain—commonly referred to as digital signal processing (DSP), their respective implementation at multi-GHz data speeds proves impractical due to excessive processor power consumption, or may even be impossible due to the absence of suitable high-speed analog-to-digital converters (ADCs) with sufficient resolution. Therefore, the majority of prior art approaches, addressing multi-Gb/s signaling, relies on analog circuits and methods—which, while potentially achieving very high-speeds, however, in nature are of relatively low performance and/or not sufficiently adaptive to cover wide range channel characteristic variations and achieve close to optimal reception. This limits the prior art effective applications to a low-index modulation schemes such as PAM2 and relatively short-reach channels with low to moderate dispersion, loss and crosstalk impairments.
Recently, a fully adaptive analog Padé filter and transceiver was introduced to overcome the above mentioned limitations. While successful in addressing many above mentioned issues, the Padé adaptive filter was not free from the deficiencies of its own. One such deficiency lays specifically in the filter cascade-based structure. When the number of cascade stages grows, particularly greater than three, which is typically required under lossy channel conditions, the parasitic effects of each stage cause overall filter transfer function (TF) degradation in exponential manner, severely limiting the maximum achievable receiver bandwidth. Other adverse effects include considerable increase in the filter coefficient values, higher output noise and the loss of signal linear dynamic range. In addition, the stage DC offset combination effects in the chain could result in significant level shifts, causing considerable signal distortions at the intermediate nodes and at the output. Some of these adverse effects could be potentially minimized, however, at the cost of substantial increase in power that depreciates most advantages of analog signal processing. Hence, it would be highly beneficial to find an alternative structure, while free from the mentioned limitations of a cascade, still capable of achieving the desirable overall analog adaptive filter properties with respect to the overall goal transfer characteristics. It is within this context that the embodiments arise.